There is a pressing need for new techniques of self-assembling small functional blocks onto a substrate. Two main factors drive this need. First, the economic of integrated circuit (IC) manufacturing is that of an economy of scale. The high cost of materials and processing must be divided among many, small functional blocks. Second, optimum device performance often requires that different functions of a device be performed by different materials, each possessing unique properties. Unfortunately, different materials can require different processing, and these materials and processes are not often compatible. Hence elements that make up a device must be assembled after initial processing.
As an example of how an improved self-assembly process can be beneficially applied to the first case, large area flat panel displays cannot be made cost effectively from single-crystal-silicon substrates. However, it is cost effective to construct large displays by mounting small, single-crystal-silicon transistors on low cost substrates. In this case the substrate must only provide electrical interconnection between transistors and mechanical support. As an example of the second case, optimized opto-electronic circuits may require the integration of silicon logic functional blocks with III-V semiconductor optical detectors or solid-state lasers. In this case, III-V semiconductor elements could function as functional blocks to be mounted in silicon based ICs functioning as substrate. Several methods and apparatuses for performing the mounting operation have been previously disclosed. All have specific limitations and shortcomings as discussed below.
A prior art approach is described by Yando in U.S. Pat. No. 3,439,416. Yando describes functional blocks or structures placed, trapped, or vibrated on an array of magnets. Such magnets include magnetized layers alternating with non-magnetized layers to form a laminated structure. Functional blocks are matched onto the array of magnets forming an assembly thereof. However, severe limitations exist on the shape, size, and distribution of the functional blocks. Functional block width must match the spacing of the magnetic layers and the distribution of functional blocks is constrained by the parallel geometry of lamination. In addition, self-alignment of functional blocks requires the presence of the laminated magnetic structure which puts severe limitations on the materials that can be used for both the substrate and functional blocks and can result in higher material cost. Furthermore, the structures disclosed by Yando typically possess millimeter sized dimensions and are therefore generally incompatible with micron sized integrated circuit structures. Accordingly, the method and structure disclosed by Yando is thereby too large and complicated to be effective for assembling a state-of-art microstructure of functional blocks onto a substrate.
Another approach involves mating physical features between a packaged surface mount device and substrate as described by Liebes, Jr. et al. in U.S. Pat. No. 5,034,802. The assembly process described requires a human or robotic arm to physically pick, align, and attach a centimeter sized packaged surface mount device onto a substrate. Such a process is limiting because of the need for a human or robotic arm. The human or robotic arm assembles each packaged device onto a substrate in a serial fashion, one device at a time and not simultaneously, thereby limiting the rate, efficiency, and effectiveness of the operation. Moreover, the method uses centimeter sized devices (or packaged surface mount integrated circuits), and would have little applicability with micron sized integrated circuits in die form.
Another approach, such as the one described in U.S. Pat. No. 4,542,397, Biegelsen et al., involves a method of placing parallelogram shaped structures onto a substrate by mechanical vibration. Alternately, the method may employ pulsating air through apertures in the support surface (or substrate). Limitations to the method include an apparatus capable of vibrating the structures, or an apparatus for pulsating air through the apertures. Moreover, the method described relies upon centimeter-sized die and would have little applicability with state-of-art micron sized structures.
A further approach such as that described in U.S. Pat. No. 4,194,668 by Akyurek discloses an apparatus for aligning and soldering electrode pedestals onto solderable ohmic anode contacts. The anode contacts are portions of individual semiconductor chips located on a wafer. Assembling the structures requires techniques of sprinkling pedestals onto a mask and then electromagnetic shaking such pedestals for alignment. The method becomes limiting because of the need for a shaking apparatus for the electromagnetic shaking step. In addition, the method requires a feed surface gently sloping to the mask for transferring electronic pedestals onto the mask. Moreover, the method is solely in context to electrode pedestals and silicon wafers, thereby limiting the use of such method to those structures.
Another approach, that combines many aspects of the previous two approaches, is that of Smith et al. presented in U.S. Pat. Nos. 5,904,545, 5,545,291, 5,824,186, and 5,783,856. These patents disclose a method and apparatus for the self-assembly of functional blocks into pre-formed recesses in a substrate. Recesses are formed in a substrate prior to the functional block self-assembly process. The self-assembly process includes mixing functional blocks with a liquid to form a slurry, and then flowing this slurry over a prepared substrate. Functional blocks randomly move in the slurry and can fall into the recesses. The forces holding functional blocks into the recesses are weak, and no means of modulating these forces are discussed or evident. Significantly, no technique of applying additional forces are provided.
A prior art approach is described by Cohn in U.S. Pat. No. 5,355,577. Cohn describes a method and apparatus for the assembly of micro-fabricated devices which employs electrostatic forces to trap the devices and vibration to randomly move the devices over a substrate to the trap sites. The electrostatic forces are generated by high voltage biased electrodes that substantially cover the substrate and are arranged as a parallel-plate capacitor. Devices are attracted and trapped at apertures formed in the upper electrode.
FIG. 1 illustrates a general arrangement of the method disclosed in the 5,355,577 patent. This figure illustrates a high voltage supply 50 powering a parallel-plate capacitor electrode arrangement with electrodes 66 and 70 substantially covering both sides of a substrate 68. Apertures 64 and 65 trap functional blocks 56 due to electrostatic field lines 72.
Limitations to this patent include a use of a parallel-plate electrode geometry and electrodes that substantially cover the substrate. The resulting geometry has several consequences. First, it requires at least three layers of materials to prepare a substrate for device trapping, a bottom conductor, an insulating layer, and a top conductor. Second, it is unlikely that the extensive electrodes used for trapping will be compatible with most finished products, hence additional process steps must be added to remove these electrodes after trapping. Further, once the trapping electrodes are removed, the trapping process cannot be reworked, repeated, without reforming the electrodes. And if the possibility of rework is to be allowed, then the trapping electrodes cannot also be used as electrical interconnects between devices, as the high trapping voltage recommended, ˜8 kV, is not compatible with microelectronic functional blocks. An additional limitation resulting from use of parallel-plate electrodes, which substantially cover the substrate, is that there is no easy, electrical means of determining when all trapping sites are occupied. This is because, in the typical applications envisioned, the change in electrode capacitance with each trapped particle is very small relative to the total capacitance of the electrodes. Hence the change in electrical characteristics is too small to detect. A further limitation resulting from use of electrodes which substantially cover a substrate and use of the suggested high trapping voltage is that a majority of the substrate is subjected to very high electric field strength, greatly increasing the odds of failure due to dielectric breakdown. Hence the substrate material and construction must be of a universally high quality, with resulting higher costs.
It must also be noted that devices will not align over apertures as claimed if the thickness of the substrate is less than ˜10 microns. Further, the high bias voltage presented is not compatible with materials of this thickness. Hence the electrode geometry claimed in the U.S. Pat. No. 5,355,577 patent cannot be construed to include the miniature and planar-electrode. The reason alignment fails is that, during mounting, devices are not ohmically connected to the top electrode, but rather are capacitively coupled. Cohn does not discuss the type of electrical connection in the U.S. Pat. No. 5,355,577 patent, but given the small size of devices envisioned, and the weak forces employed, achieving an ohmic connection is not tenable.
In the U.S. Pat. No. 5,355,577 patent, Cohn also discloses an alternate embodiment using a multitude of planar electrodes to form a negative dielectrophoresis trap. The method attracts functional blocks to regions of relatively lower electric field strength. However, a limitation exists during mounting in that functional blocks must have a lower average dielectric constant than that of the surrounding medium. Furthermore, the required electrode configuration is complex and must cover the entire substrate surface. Hence all the limitations discussed above regarding “electrodes that substantially cover the substrate” still apply here, plus limitations regarding the additional complexity of the electrode configuration.
Finally, there are many previous art disclosures that employ electrostatic chucks for various uses. Most are employed to hold a silicon wafer during IC processing, see for example, U.S. Pat. Nos. 4,184,188, 4,724,510, 4,520,421, 5,539,179, and 4,962,441, and are not amendable to mounting sub-millimeter size functional blocks. Another use proposed for electrostatic chucks is to deposit particles for chemical and pharmaceutical manufacture, U.S. Pat. No. 5,858,099. While they do employ electrostatic chucks, these disclosures do not apply to the present application.
Even with the techniques above, the concentration of functional blocks upon regions of receptor sites is not good enough. Several passes of the web through the self-assembly process is required to completely fill all of the receptor sites. In the U.S. Pat. No. 5,355,577 patent, the functional blocks only move about in a random fashion over the substrate. Thus, it is difficult to control the incident of the functional blocks upon the receptor sites.
There remains needs for rapid and efficient mounting of one or more small functional blocks on a, potentially large, substrate, while using materials, processes, and structures that are easily and economically integrated with existing flat panel display and microelectronic manufacturing processes.